1. Field of the Invention
The present invention relates generally to integrated circuit fabrication, and, more specifically, the present invention relates to the fabrication of a super self-aligned collector for a bipolar junction transistor device design and process flow that allows for a compact bipolar junction transistor layout.
2. Description of Related Art
A bipolar junction transistor (BJT) exhibits significant resistance and substrate capacitance that raise performance issues. In high-performance bipolar complementary metal oxide semiconductor (BiCMOS) processing the process flow needs to be integrated. The addition of high energy, high dose implantation, the use of a heavily doped substrate layer, and the use of high temperature cycles all significantly degrade CMOS performance. Independent optimization of the deep collector plug (DCP) implant and the buried layer (BL) is difficult especially in the presence of CMOS devices.
FIG. 9 illustrates an existing BJT 10. The BJT 10 includes a substrate 12, a collector structure 14 disposed in substrate 12, a buried layer 16, and deep trench isolation (DTI) structures 18. BJT 10 also includes shallow trench isolation (STI) structures that include a collector-proximate STI (collector STI) 20, a middle- or emitter-proximate STI (emitter STI) 22, and a base-proximate STI (base STI) 24. Upon substrate 12, an epitaxial layer 26 is formed. An emitter stack 28 is disposed above the epitaxial layer 26. Additionally, a deep collector plug 30, a collector tap 32 and a base tap region 34 are part of BJT 10.
Total resistivity from the collector structure to the collector tap in a BJT has a significant effect on performance. In FIG. 9, three significant resistivity paths exist. Although each path is depicted schematically by a dashed line, it is understood that the resistivity paths are actually located in 3-dimensional solid space in substrate 12 that is approximated by the dashed lines. A downward vertical first resistivity path 36 passes from collector structure 14 into substrate 12 toward buried layer 16. First resistivity path 36 may amount to about 10% of the total resistivity between collector structure 14 and collector tap 32. A horizontal second resistivity path 38 passes from first resistivity path 36, under emitter STI 22 and toward deep collector plug 30. Second resistivity path 38 may amount to about 30% of the total resistivity between collector structure 14 and collector tap 32. An upward vertical third resistivity path 40 passes from second resistivity path 38 into collector plug 30. Third resistivity path 40 may amount to about 60% of the total resistivity between collector structure 14 and collector tap 32. For example first resistivity path 36 represents a range from about 300 ohm·cm−2 to about 700 ohm·cm−2, second resistivity path 38 represents a range from about 1,300 ohm·cm−2 to about 1,700 ohm·cm−2, and third resistivity path 40 represents a range from about 2,750 ohm·cm−2 to about 3,250 ohm·cm−2.
Direction changes in current flow also affect efficiency. Accordingly, because of the downward first, horizontal second, and upward third resistivity paths, efficient current flow also is detrimentally affected due to directional changes.
FIG. 10 is a top layout schematic view depicting selected structures of BJT 10 without depicting elevational differences. A BJT perimeter 42 measures the BJT 10 from the outer edges 44 (FIG. 9) of collector STI 20 and base STI 24. Emitter STI 22 and base STI 24 are part of a guard ring that is encompassed by BJT perimeter 42. An exptaxial base layer perimeter 46 is also depicted that relates to epitaxial base layer 26 in FIG. 9. Emitter stack 28 is depicted by its perimeter, and an intrinsic base region 48, is also depicted by its perimeter as it forms substantially above collector structure 14. Other selected structures include collector tap 32 and a base tap 50 portion of epitaxial layer 26 that is located within epitaxial base layer perimeter 46. It is noted that current flows through substrate, beneath emitter STI 22.